Last semester I wrote some of the basic components of a lattice processing simulator. These past couple weeks have been full of digressions, but I'm back to coding 4-8 hours a day. I've been developing a Scheme Web Server and XMLHttpRequest handler which should enable web-based development for a fabric of cells (email me if you want the code in its current form). I had some problems with POST method, but I've since figured it out.
My current plan is to build up an interface that allows me to modify code and provides a clean graphical interface to a the system. After the development environment is working and I have an FPGA board exposed to the internet, I will host the system on an FPGA board to start coding the hardware scheduler.
I've also been cooking up the system to compile Scheme to LUTs. Scheme's "bit-string" abstraction is very useful for encoding LUTs. A brief summary example of the LUT definitions:
(define (lut configuration in)
(if (bit-string? cofiguration) configuration (unsigned-integer->bit-string configuration))
(define (lut2 configuration in1 in2)
(lut configuration (bit-string-append in1 in2))
(macro-define '(name configuration)
'(define (name in1 in2) (lut2 configuration in1 in2))
'((zero2 0) (nor2 1) (pbq 2) (pb 3) (pqb 4) (qb 5) (xor2 6) (nand2 7) (and2 8) (nxor2 9) (q 10) (pborq 11) (p 12) (porqb 13) (or2 14) (one2 15)))
I have written about 8 pages of stuff demonstrating how to compile functions to a hierarchy of LUTs using this abstraction with let to assign temporary names to internal pins. When these functional descriptions get merged with the lattice processing model I will be able to simulate state evolution and delay. I will need to add an algorithm to infer an n-input LUT for arbitrary n-input combinatorial functions in order to map to real hardware.