Friday, September 29, 2006

Coupling FPGA and Multicore

article in the register.
another article in the register.

"The end result will likely be a multi-core world where the common general purpose cores of today sit alongside FPGAs, networking products and other co-processors tuned to handle specific tasks at remarkable speeds."

1 comment:

raja neogi said...

The FPGA vendors look at this slightly differently -- Mix and match hard-IP with soft-IP to build an application story.

The hard IP is defined by readily availavle cores (e.g. Power core or arm core), serdes blocks, ddr blocks etc.); while soft-IP is all the emulation you hear about frequently (e.g. multiple microblazes built using fabric resources and a few CLBs left over to implement those vexing loops).

In theory, all this falls under conventonal SOC design; the part that is new is the reconfigware -- that is specialized resources to allow rapid reconfiguration, I mean dynamic reconfiguration.