In September I wrote:
To optimize for static currents, using dynamic threshold scaling (modulating the body bias voltage of the chip) along with dynamic voltage scaling [for active power] seems to be a viable technique. Here's a spreadsheet model (ODS original) for leakage current in a transistor varying Temparature, power and threshold voltage across a reasonable range.
According to this FPGA Journal article, Altera has incorporated programmable body biasing into the logic blocks of their 40 nm Stratix IV FPGA.
Xilinx will probably also follow suit with dynamic threshold scaling sometime this summer.
Altera claims to have 680K logic elements in their highest capacity offering... I think 640K is all anyone will ever need :)