Google's Weakness: User Experience

Paul Graham pointed out that someone could take advantage of Google's UX weakness in his article identifying a new search engine as a potentially disrupt-able industry for a highly ambitious founder.Google might not realize this, but they have a huge gaping weakness in User Experience. I have one Facebook account. I have 6 or 7 Google accounts. And they don't work well together. When I am trying to access my adwords, I need to sign in with my amirmotion gmail account using my zigfu.com email address as my login, and then I get this error because I'm still signed in to my catalystac.com account:

So in order to use Adwords, I need to log out of my catalystac.com google account and sign in with the appropriate gmail account, which for adwords, is zigfu.com. Due to my multiple accounts setup with Google, I have the same awful user experience with just about every google app. For blogger and youtube I need to use my amircatalystac gmail account (which is different from my catalystac.com account). I also have no idea how to access the admin panel for my catalytac.com domain, so I periodically can't access the documents that people send me in Google docs. Here's what I get when I try to click "Yes" to a google calendar request for RSVP in anything other than my tinkerheavy.com Google account:

My iPhone provides the only/easiest way for me to aggegate all these obnoxious multiple Google calendar and multiple Google email account issues and provide me with a single amir-centric user experience. Instead of this sort of awesome and consistent user experience, Google offers me MULTIPLE USER ACCOUNT HELL. The other issue with Google is there is no button I can push to send an email to complain to Google about my terrible user experience or to get support with improving it. Larry Page should be reading such an inbox, because this is a huge weakness for Google and they probably don't even realize how bad it stinks.

OpenCL/CUDA for FPGAs

I noticed Altera announcing OpenCL support for FPGAs. Here's a paper and some slides on it. I also noticed a blog pop up last week about doing OpenCL on Xilinx. There's also been work on a CUDA->FPGA system called FCUDA from a group from UIUC and UCLA (here's the longer paper on FCUDA). So hardening GPU-designed algorithms is now at least an idea, and possibly a good one. This will enable CMOS array sensors with integrated ASICs performing computer vision.

Making a TV for Steve

The TV space is ripe for disruption, and I keep seeing speculation about an Apple Television. In his biography interviews, Steve Jobs claimed to have "finally cracked" the TV user experience.

Last week I presented my start-up ZigFu at the Microsoft Venture Capital Summit and said that motion-control technology like Kinect will be as disruptive to the TV as the remote-control or possibly even color (Video at the end of this post). We want to make a TV with a motion-controlled user experience that would have made Steve Jobs proud to demo it. A TV designed for Steve would take you no more than a few gestures to watch a movie, or search for a video or song. You'd never be that far away from Netflix, Amazon, eBay, or even ordering a pizza with gestures.

In addition to a world-class TV user experience using gestures, the other major differentiating factor for success in the gesture controlled smart TV race is an app eco-system. It's forming now. You might have noticed the storm of Kinect-hacks coming out of academia or indie studios. You might also have read my other posts that I am running a fresh-out-of-YCombinator startup supporting developers with UI libraries, tools and an app-store for motion-controlled apps.

I may be stirring my own kool-aid, but I feel like I aught to put a stake in the ground now, especially while I'm busy hustling to find investors (contact amir at zigfu.com). At any given time, there's only a few next-big-things in technology and right now motion-control is one of them. Kinect was huge, and from the insider's perspective it looks like there's a tsunami coming that will transform the way we consume and interact with media.

The next wave of computer-user interaction to come after touch will be motion. We will take for granted that computers can see us and react to our movements. Motion will be a defining feature of the smart TV category in much the same way touch was to smart phones. Motion, combined with voice and smartphone control, will be as ubiquitous as the remote control.

The evolution of TV will have apps like Facebook, Skype, and Youtube and of course features like video sharing. These applications will make TV a more social experience (this post is fully buzz-word compliant). Where these apps would kinda suck with a remote, these new apps plus all the existing cool features we already have on TV can be made much better with motion-control. Football fans know what I mean when I say I wish I could play replays with something better than the remote. We want to reimagine the DVR experience with motion-control. Many totally new applications will emerge in this eco-system as well. We are already seeing several groups making applications for trying on clothes in a virtual fitting room and playing motion games that will be bought through an app-store.

The network is mature enough for these applications to emerge. The technology exists so that we can build it all today, but it is not yet accessible to developers. We're still at the beginning of the development of this control paradigm and we haven't settled on best practices for interacting with devices with gestures. Kinect needs something like Cocoa to provide lists and menus. That's what ZigFu is building.

Tracking the nerd news on the inter-tubes, I've noticed an onslaught of press releases about Xbox Live with TV channels and Kinect control, and several other companies with controllers using Wii-like controls. Speculation is abound that some Apple Television product that may eventually be announced with voice-control features like Siri. Maybe Google will play in this space and provide a motion layer to their Google TV offering: with Motorola they acquired a major player in the set-top-box space. We think this eco-system is new and different enough from anything that's come before it. Perhaps our start-up can run with the flag and beat the big guys to the market.

Once it is obviously a differentiating factor in TV sales, all the vendors will embrace the category of motion controlled smart TVs with apps and games. Some combination of a camera and microphone array will be integrated into every television and your smartphone or tablet touchscreen will be able to talk to the TV too to transmit control signals.

After I presented at YCombinator's demo day, someone approached me and said "your demo has Apple written all over it." And that's pretty much what we set out to do, we're making a TV for Steve.

Here's a video of my presentation about the work we're doing at ZigFu:



My demo isn't totally polished yet, but you can see where we're going.

ZigFu - Motion Apps

Well, the cat's out of the bag. We've been doing YCombinator this summer developing a motion apps company we're calling ZigFu. Something's gotta pay for all the lasers...

Today was the YC demo day and we got some nice press today in GigaOM and Forbes which put us on their short-lists.

And that's one demo day down... still another one tomorrow, but now they'll already be anticipating something awesome so I'm probably going to have to turn it up to 11. Maybe I'll do the Hokey Pokey for them (we had Paul Graham do the Hokey Pokey during our YC interview ;)

So what's ZigFu (for great justice). This blog has a bunch of post showing the Unity bindings for OpenNI. Over the summer we've built a set of UI Components for developing apps using motion control and the plan is to launch a portal for motion apps next.

The goal here is to integrate a ton of existing computer vision stuff into the OpenNI framework so we can track hands and skeletons and faces. We think the motion sensing technology will make a whole new market for smart TV apps, and we're forming the platform-independent vendor required to make the application layer that sites above the hardware and computer vision middleware.

We want to make the remote control obsolete.

The Persistence of Data: Why the future is write-once

I went to an interesting discussion called "Big IT meets Big Web" today hosted by Battery Ventures which brought together a bunch of nerds to talk about the harmonic convergences of IT and Web worlds and deploying services in the cloud. One idea that struck me, was that many of these companies have huge data stores that are never erased. This means we have too many features in the magnetic disks and solid state drives we are using today: they do not need to be erasable/reprogrammable. The vast majority of data storage they need is "Write Once Read-Many" or WORM.

Crystal ball: in the near future, reprogrammable flash ROM will be replaced with write-once PROM. PROMs will be cheaper if designed as a write-once fuse array structures. A crossbar and fuse-array can be higher density than a floating gate flash ROM design. It may also require simpler processing steps--though the row decoder and sense amplifiers required for both types of storage may be the determining constrain in that regard.

Cutting with Kinect

( tinkerheavy.com ) Using Kinect to make Little Red Riding Hood cut up stuff. Fruit Ninjas and Veggie Samurais better get ready for the Sushi Wars.

I'm using the Object Slicer package and my Unity wrapper for OpenNI.NET / Kinect.

Kinect Poi

Unity + Kinect + RopeScript = Mace

More Kinect Hacking

(tinkerheavy.com) This is a demonstration of the Unity wrapper for OpenNI. My skeleton is tracked as I move in front of the Kinect. My feet are rigid-bodies that can kick the boxes. The boxes are also carryable if two hands interact with it simultaneously.

If you already have OpenNI+NITE working with your kinect, the binary for this project (pc and mac) is here:http://tinkerheavy.com/unityskeleton.zip
To get the others working you'll need to get OpenNI and NITE from OpenNI.org (to use the kinect get sensorkinect from https://github.com/avin2/SensorKinect instead of the openni.org sensor module)

The code and unity project are available on my git:
https://github.com/tinkerer/UnityWrapper

Kinect Hacking

I've been hacking the kinect for the last few days. This Little Red character was developed for an upcoming iPad interactive story from my company Tinker Heavy Industries.



We've done this with a few other characters. There are some issues with the joint orientation which means my arm goes up and her arm goes down...

Intel Atom, now with an Altera FPGA!

/. points to this article which says that Intel is putting together an Atom and an FPGA into a single package and selling it for somewhere in the $61-100 range in lots of 1000. This is Intel competing with ARM for the embedded space. We all saw the tighter integration of x86 and FPGA coming 5 years ago when hard PowerPC started finding their way into Xilinx V2 Pros. Achronix is already using Intel to fab their components. In a year or two, perhaps we'll start to see x86 and FPGA on a single die by Intel and then a few more years and we won't need the x86 anymore.

This is just starting to heat up.

I looked at the FPGA they put on board, the Arria II GX FPGA.

25,300 ALMs
63,250 equivalent logic elements
50,600 Registers
495 M9K memory Blocks
791 Kb MLAB Memory
4,455 Kb Embedded memory
312 18x18 multipliers.

I don't remember Alteras logic modules anymore (some sort of big 8 input logic thing), but this chip is like 1/20 of the size of big FPGAs on the market today, though it has an impressive supply of multipliers. Clearly going to be a champ for custom video codecs since it'll be able to do tens of billion of multiplies per second when you need it to.

Hopefully this strategy works and then Intel will experiment with Xeon + Achronix Speedster on a single die :)

PS: My little girl is walking:

Little Red also walks on the iPad too, but so does the Big Bad Wolf! (buy our letter tracing iPad game for kids!)

Ten Things to do with an EC2 GPU

Yesterday I was saying we'll see crypto cracking on EC2 with GPUs. In addition to writing it on this blog, I enthusiastically proposed it to friends who are into this sorta thing and of course we then discovered that someone already did it so we lose all novelty points now and should just go back to thinking about how to make money using cloud based GPUs.

I've been writing about this for five years already and I think EC2 with GPU is like an invitation for me to take my GPU accelerated spreadsheet work into the limelight. A good question is, does Amazon have the capacity to turn that $2.10 per teraflop per hour into $2100 for a Petaflop for an hour? Can they provide it with enough granularity to provide a petaflop for a minute for 2100/60 dollars? I also suspect that some data intensive applications will wish they had solid state disks and faster connections between nodes (as I understand it they have 10Gbps links now). How will we deal with streaming data sets to and from the server? I wonder if you might be reserving the GPUs even when you're not using the GPU, but just moving data to and from the server; this would be a wasteful use of resources.

So here's my list of ten things to do with an EC2 GPU instance.

1) Electronic Design Automation - Giving supercomputer resources to teams of 2 or 3 designers for electronic simulation and synthesis. We definitely want some FPGAs in the cloud for logic simulation and other non-GPU algorithms that FPGAs are good at like pattern recognition. FPGA tools have a way to go and the appliances will need a GPU cloud just to do P&R.

2) Render Farms - NVidia's bought Mental Ray probably knowing they would put Reality Server on EC2. Plugins for Photoshop and Maya are gonna be next; lower resolution screen captures

3) Video Games - A system that renders in the cloud and streams it to your mobile device? Obviously other people are doing this, but access to the Amazon takes the risk out for developers! We can have much much much better game graphics, but controller to screen round trip latency puts an even higher burden to get the computation done faster.

4) Financial Services - Remember when you got to take a 15 minute break after starting a big Correlations or Monte Carlo sim? I wonder if we can get low latency streams of market data and make a sandbox for high frequency traders.

5) Voice Recognition - You know when you're talking to those computer on the phone and it acts like it can recognize you? Not sure how to pipe that volume of data in though.

6) Face Recognition - Soon to be a facebook feature for sure: we can index your face and then auto-tag you.

7) Search for Extra-Terrestrial Intelligence - Actually don't.

8) Computation Molecular Dynamics - Folding on a cloud!

9) Crypto Cracking - If only you had some crypto worth cracking you now have a supercomputer! You could also factor some big numbers, isn't RSA offering money for factoring some big numbers?

10) Verifying Goldbach's Conjecture - We seem to be having trouble proving that every even number is the sum of two primes, but computers keep verifying ever increasingly larger number we throw a them.

$2.10 per teraflop per hour on a $3000 GPU which consumes about 10 cents of power per hour means there's plenty of room for profit and competition in the infrastructure side. I suspect some of the algorithms above can still be designed as services that take advantage of these economics. Unless cloud-based GPUs gets more competitively priced, I suspect anyone selling GPU-accelerated services with constant enough demand would want to use their own server and possibly only tap into cloud resources when they are in need of capacity.

GPGPU on EC2

Looks like you can get some NVidia Teslas in an EC2 instance now! It seems like Amazon is in the business of selling you a teraflop for $2.10 per hour. This is going to be a big competitive business. I presume I can get a petaflop for a few minutes for under a hundred bucks. Time to start making crypto-crackers!

First Product

In June, I started a company to make apps for kids. Now Tinker Heavy Industries has its first app in the app store:

Another educational app to teach spelling is currently awaiting Apple's approval. Our next app will be an interactive Little Red Riding Hood. We've done some work learning how to build touchable characters and environments. Here's a demo of me playing with Tinker, our multi-touchable ragdoll elephant (made in Unity):



Periodically, I find myself falling back to the usual musings of semiconductor physics and mathematics. Here's a ring oscillator. The PMOS width's probably need to be relatively bigger for it to be useful and I don't have any representation for the wells or a simulation including parasitic BJT's (my imaginary SOI process avoids latch-up by using magic!)



Naturally I've also been playing with Mandelbrot sets, bifurcation diagrams, audio synthesis, and Riemann Zeta function partial sums. I'll have to put up some videos of super nerd stuff later.

Here's Star's face 3-D scanned and imported into Unity!

Career Change

Since 2007, I had been developing a PDP-11/70 emulator using Virtex-5 FPGAs for Quickware. The QED970 system is composed of several boards designed to be compatible with legacy hardware specifications. Designing a replica of a 1970's machine revealed a lot to me about the way it used to be; I can hardly imagine designing entire boards with LSI and MSI components to be a Floating Point Unit. An entire generation of computer scientists learned PDP-11 Assembly: now it's like Latin. So I gave an old soul to a new machine, where now?

For the few months before June I went traveling: first in Mozambique and South Africa for an Adventure and then in Israel to be with my family and apply for a position at Brightsource doing accelerated computing work. I was very impressed with the company when I visited last fall. I believe that Brightsource's approach to engineering better solar power plants will be successful at achieving grid-parity with coal after a few iterations of the design. This spring I went back to Israel fully intent on building a supercomputer for designing solar power plants.

I came back to the USA by way of San Francisco, to visit friends and go to a wedding. Instead of working on supercomputing, I have decided to move to California and make interactive stories and educational games for the iPad. This is a wide departure from where I thought I would be. The timing is right and I think anyone with a sense of "the next big thing" see a future where paperbacks will be quaint like vinyl, with an underground scene who "just miss the feeling of paper in my fingers." I'm starting the company with good people and we are going to make the highest quality children content available. In a few years the big heavy backpack full of school-books will be obsolete.

I fully intend to continue posting to this blog about accelerated computing and semiconductors. I haven't given up on developing a spreadsheet system that runs on GPUs and FPGAs. I just want to be able to fund it myself. I think that I'm also going to be more open about my accelerated computing ideas on this blog now too, I'm trading the fear that someone else will steal on of my ideas for the fear that I might never fully express them.

GPU Supercomputing Rundown

/. linked to this opinion article on AMD, Intel and NVidia in the next decade (full disclosure, I own shares in NVidia). Some of the opinions about OpenCL and CUDA are the same as I expressed in my post about Intel purchasing RapidMind and Cilk. Since I made that post, Intel has decided to abandon plans to release Larabee as a consumer GPU. This was not a big surprise, since Larabee could not compete with AMD's HD 5870 or 5970 products. The consumer GPU space is currently dominated in terms of teraflops per dollar and per watt by these AMD/ATI cards. NVidia still dominates the GPU computing market because their investment in CUDA. AMD was the first to support OpenCL, but OpenCL seems more and more like an also-ran API. AMD was also the first to support DirectX 11, but NVidia downplays this.

Adobe is going to support CUDA in their tools. I don't know how AMD is going to turn the GPU supercomputing market in their favor: hardware leads are not enough except perhaps in the highest of high-end supercomputing applications.

NVidia's move to make their new 40nm Fermi architecture with a behemoth 3B transitors has proven troublesome with yields reported in the single digits. Reports inidicate that Nvidia will disable disfunctional stream processors similar to the way IBM boosted yields of the Cell processor for the PS3 by enabling only 7 of the 8 SPE processors.

It seems like there will be an increasing trend towards defect tolerant designs and design-for-yield EDA tools; once upon a time, I had an offer to intern at IBM developing such a tool. A number of issues at smaller geometries arise such as variace in wire dimensions and gate-lengths affecting the switching speed. Also, with more components in a chip there is simply more that can be broken. Possibilities for yield enhancment include disabling cache regions, lowering individual core speeds, and disabling disfunctional cores entirely.

More on SaaS and EDA

EDA SaaS has been a recurring topic on many of the blogs I follow. Harry (the asic guy) wrote about the Blooming of an EDA SaaS Revolution in his first post at Xuropa. He says that the revolution "depends on a confluence of critical technologies." He also writes that the coming revolution will level the playing field allowing smaller EDA firms to compete. The same economics of sharing model that creates SETI-like distributed computing, fab-less semiconductor companies, and open source software has the potential to impact the EDA industry in a big way. I suspect the effect of decreasing the barrier-to-entry for design tools will ripple into the broader electronics industry.

With SaaS, the fixed cost of high performance computing infrastructure transforms into a variable cost. For a lean team of engineers, this can decrease the cost of compute resources substantially: who needs a $10,000 server, when you will only need to use 5000 CPU-hours on it which costs half the price from a cloud provider with the added bonus of being able to use 100 CPUs simultaneously on demand. This kind of computing power can increase the throughput of large complex simulations and optimizations substantially. I am currently paying for software licenses and infrastructure, but I would much prefer an on-demand high performance computer to run my simulations.

SaaS providers do not necessarily need to host their own infrastructure and can outsource some or all of their infrastructure requirements to third parties. Communication latency, job-size and job-work are the major factors determining how closely coupled a distributed computation network must be. If the data transmission for each job is order N and the work to process this data is N^2, then the communication-latency factor becomes negligible as the data transmitted increases. Large correlation operations like SETI are practical over large scale distributed networks for this reason.

Raw high-latency compute power can be provided by a widely distributed cloud: instead of searching for ET, your PC can help me make timing. Certain companies will pay to use your machine for distributed computing projects. These companies may act as a middle-man broker leasing out computing power in schedule blocks to a SaaS provider. Certain SaaS providers, recognizing that their customers work at 2-6 AM, may purchase large blocks of cheap computing power in these hours in each time-zone for example. They will have to form agreements with other cloud infrastructure providers to handle cases of excess demand. This forms an interesting set of insurances and contracts among the infrastructure providers, SaaS providers, and end-users. For example, an infrastructure firm may have unreserved excess capacity which it leases off for short intervals at short notice for low cost. If an end-user requires a large supply of CPUs for a long interval of usage on short notice they will pay a premium for this. To simplify matters, a SaaS provider takes jobs from users who have purchased a certain number of CPU-hour "tickets" in advance. These tickets have expiration dates and exchange values depending on whether you want 3600-CPUs-for-a-second or 1-CPU-for-an-hour.

For the software providers, supporting hosted applications is different from supporting installed programs. Issues are much easier to isolate: since none of the users ever install the software, if something is broken with the user's experience, it is definitely the fault of the software provider and not a virus, out of memory error, or other hardware incompatibility. Suppose the EDA industry wanted to support Multicore, FPGA or GPU accelerators for certain tasks. If they hosted this accelerated infrastructure to provide their software as a service, then they wouldn't have to deal with hardware compatibility issues providing this software to third parties.

Product iteration can be much faster since new features can be tested without requiring users to install anything. Additionally, all bugs can be reported back to the developers without requiring any action from the user. And of course, you shouldn't force new features on people or you'll have the same negative response that happens whenever Facebook changes their layout or adds new features. Facebook users can't complain with their checkbook (join my "Leave Facebook when One Million People Join This Group" group).

Security policies of EDA end-users are frequently cited as the major barrier to SaaS, indeed the sole criteria to reject using a hosted provider model. If secrecy is an important factor for a design, it is unlikely that a SaaS tool will be used. This is not due to some fundamental security issue with hosting an application remotely instead of locally. This is mostly an irrational insecurity of users that think it is harder to break in to their locally hosted computers versus a remote facility. Indeed large remotely hosted virtual private networks may even have better security than anything locally hosted because a large infrastructure provider can afford to deploy more attention to the problem.

Still, because of this paranoia, FPGA design teams and tools will be the first to transition to SaaS. I suspect that FPGA design teams value secrecy less than lowering fixed costs and lowering simulation latency, and secondly because the FPGA tools are used by many more people than ASIC tools. Of course tools like a distributed digital logic simulation engine will be useful in both ASIC and FPGA design.

The effect of decreasing the barrier to entry for electronic design tools as well as decreasing the latency of a simulation will lead to more people making more designs. The availability of more reconfigurable logic designs increases the value of the FPGA in a superlinear way. The total value of programmable logic cores derives from the various ways they can be combined: thus the value of the FPGA grows superlinearly similar to Metcalfe's Law.

So how will this happen? A fairly clear vision is shared by enough people blogging about EDA SaaS. The EDA industry certainly must be paying attention to the cloud computing meme and what SaaS means for their industry. Unfortunately, the economic barriers to entry are only a small aspect of the problem facing the programmable logic market. FPGA tools need to be more accessible to non-expert users. My vision is a tool flow combining incremental synthesis with dynamic partial reconfiguration that lets you program your array just like a spreadsheet.

Altium Nanoboard 3000: Day 1

I received an Altium Nanoboard 3000 with the condition that I provide feedback on my experience using it. I hope this information will be useful to Altium and to other Nanoboard users.

This will be the first in a multi-part series about using the Altium Nanoboard 3000 with the specific angle of teaching a total FPGA newbie how to get started with this board.

A friend of mine is a senior in MIT's Aeronautical Engineering department. He has to build a UAV for a class project and wants to use an FPGA to control servos. He asked me to teach him how to use FPGAs. I told him I was getting a new board aimed at providing a good user experience to newbies like him and that I would teach him how to use the board. We started to install the Altium Designer software on my friends dual-core laptop. "Should we read this license carefully or just accept it like we usually do?"

Eventually the Altium Designer completed installation and we started it up and figured out how the board-tied licensing works.

Our attempt to use the board was thwarted by a massive hard drive space requirement and extremely large download size of the Xilinx development tools. Installation of the webpack wasn't worth the time to clean up space on his PC and then download 5 GB on a computer which would rarely have the Nanoboard attached. I decided to install the Altium and Xilinx software on my own laptop and become familiar with using it before trying to pass it off to a newbie. My laptop is a single core (Pentium M), 1 GB RAM, Toshiba Satellite R10 tablet recently reformatted with a fresh install of Windows 7 (which broke a bunch of things, but is fine overall). Altium installed in about 24 minutes from the DVD and I left the Xilinx Webpack to download and install over a few hours while I did something else. One of the optional Xilinx DSP tools failed because it does not support Windows 7.

This Xilinx-dependency isn't necessarily Altium's fault, but if they're trying to focus on user experience, they aught to figure out how to make this all actually work without requiring multiple hours of downloading and installing. The DVD case provided seems more expensive than a USB key that could fit all the required software pre-installed on it. Frankly, I'm tired of software installation processes, my writings about EDA SaaS perhaps point to a better way: provide all the software on a remote host, give me a small 1 MB bitstream downloader to run locally and let's get on our jolly way already. Maybe a 10-20 MB maximum download and install size if you want to include some complex software locally near the board like an in-circuit-debugger. Xilinx's software downloader and installer requires 90 MB before you even start installing the rest of the 6 GB. I just don't see why it is technically necessary to download and install multiple Gigabytes of data before I can start pumping bitstreams down a USB cable.

Altium Designer System Requirements indicate that it was not designed to run in 1024 x 768 resolution and indeed several of the dialog boxes are cut off without ability to scroll or resize. My system barely meets the rest of the minimum specifications. I will probably have to install this software on a better system, but I do not have easy access to one now.

So I have installed all the required software from Altium and Xilinx onto my laptop and finished all the license registration setup with Altium and Xilinx. I'm about 20 seconds into the "Simple LED driver" demo video in the "Training Room" video set and I cannot insert a new schematic into the project as shown in the demonstration video. If I add a new VHDL file first, I can then insert a new schematic. I can then remove and close the VHDL file leaving just a schematic in the project. To isolate the problem I created a new project and attempted to add a new schematic and failed a few times. I repeated the VHDL insertion and then adding a new schematic had no problem. I restarted the Altium Designer and created a new project, and then attempted to add a new schematic: it failed again. The VHDL-followed-by-a-schematic trick works again. I just sent an email to Altium describing this bug.

Certain hints are missing from the first tutorial video which would really be helpful for first time Altium Designer users: "hit spacebar to rotate a schematic symbol", "hold control while dragging a block to extend the bus connection", "right click to terminate a bus line without attaching it to a port." Overall, the video is informative enough, and the help search is enough to someone who has done this before and knows the lingo (example: "net label" is a meaningless term to someone who has never designed electronic systems).

3:45 seconds into the "Simple LED Driver" video, I am told to be patient for the Xilinx tools to finish running. A few minutes into the build process, the Xilinx Mapper fails with this error:

INFO:Security:56 - Part 'xc3s1400an' is not a WebPack part.
INFO:Security:61 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:63 - The LM_LICENSE_FILE environment variable is not set.
INFO:Security:68 - Please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
ERROR:Security:9 - No 'ISE' feature was available for part 'xc3s1400an'.
ERROR:Security:12 - No 'xc3s1400an' feature was available (-5).
----------------------------------------------------------------------

This is an unfortunate error message to get because the Altium Nanoboard resources page has a clear link to "Download Xilinx ISE WebPACK 11.1." Unforgivable.

I ran the Xilinx License Configuration Manager to get a 30-day node-locked evaluation license so I can use target the FPGA on the NanoBoard with my laptop for 30 more days. My Altium Designer license lasts until next year though, so either Altium will have to get me another gift or I'll have to see if I can use my license for ISE at work on my laptop: though for my work I run Xilinx tools on a beefy machine over a remote desktop connection on a VPN and I'm not sure if the license can be transferred or otherwise used by my laptop. I will not be installing Altium Designer on my work computer since the license is tied to the NanoBoard itself.

After setting up the 30-day-node-locked-evaluation-license from Xilinx, everything runs as expected and as demonstrated in the video: I can control the boards LEDs using sliders in Altium Designer on my PC to control the Red, Green and Blue values. Very satisfying effect, and after all the initial bumps I look forward to exploring rest of the tutorials, at least in as much free time as I can scrounge between now and when my temporary evaluation license of ISE expires.

Overall first impressions: Altium has not field-tested the user experience of the NB3000 on an FPGA-n00b. Since I am being their guinea pig I feel like I have to be pretty explicit about how my experience deviates from the marketing claims on their website. Let me break down their claims and give you my verdict:

"Not your average FPGA-based development board" - definitely above average. This board has decidedly more sex-appeal than any other I have received in the past. It even has MIDI I/O already soldered on the board so I don't need to go out and buy an optocouper and a female connector to make MIDI synthesizers.

"you don't need any FPGA design experience to use it" - I sincerely doubt that someone without Xilinx already installed could get through the installation and licensing in less than 5 hours. Assuming the installation and licenses are already set, I don't think a newbie can get through the first 4:35 Simple LED Driver demo video in less an hour. The video should be drawn out to make each step even more explicit (how to make bus connections, rotate schematic symbols, etc). Now that I've taken care of all the licensing, I will see how my Aeronautical Engineering friend gets through the first tutorial video.

"Simply install the software, connect the NanoBoard and you're ready" - Ready to get frustrated with the Xilinx webpack installation. And then get frustrated with the Xilinx license. The initial user experience with the NanoBoard still needs some polish, and I think this article will help them with that.

Intel Buying Everyone

In the past month, Intel has purchased RapidMind and Cilk. I've talked about Cilk on this blog a while ago (post has comments from one of their founders).

This was a good move for Intel. It is probably an attempt to make the eventual release of Larrabee less painful for developers. This will help put Intel in the leader seat for parallel programming platforms.

What will this mean for CUDA and OpenCL? (Full disclosure: I own shares in Nvidia).

RapidMind and Cilk are both easier platforms to use than Nvidia's CUDA, but the total number of available Teraflops in all the CUDA-capable nodes makes it attractive. Intel still needs silicon to compete with CUDA. RapidMind and Cilk will give Intel's silicon a lot more flexible programming model than CUDA gives to Nvidia's GPUs, complementing the fact that Intel's silicon will be a lot more flexible architecture than Nvidia GPUs.

Cilk and RapidMind will simplify some of the work of parallelizing library functions, but Intel will be hard-pressed to compete with Nvidia in cost/performance ratio in any application with a strong CUDA library. Nvidia GPUs are already cheap: Intel will have to use their insane operating leverage to compete in the accelerator market on a cost/performance basis. Intel can also win this market from Nvidia by getting their latest integrated graphics chips in all the newest machines and generally by doing things that piss off anti-trust prosecutors.

I'm not very hopeful for OpenCL. Unless Nvidia decides to abandon CUDA or make isomorphic with OpenCL, then OpenCL is DOA. Apple's dependency on Intel means they will eventually find Zen in whatever platform Intel offers them. AMD is the first, and will probably be the only one to support this "Open Standard" for GPGPU and multicore. Unfortunately, they will find themselves the leader in a very small market. AMD needs to focus on crushing Intel in the server market by getting to 32 nm first and releasing octo-core Opterons.

This will be interesting to watch unfold.

Power vs Speed

It would appear that we have reached the limits of what it is possible to achieve with computer technology, although one should be careful with such statements, as they tend to sound pretty silly in 5 years - John von Neumann, 1949

The design goals in parallel computing differ between the embedded multicore market and the high performance computing market. On the one hand, more cores can do parallel work and get a job done faster, while on the other-hand power efficiency can be increased with no penalty to throughput by doubling the number of cores and halving their clocks. Both switching power and leakage power can be optimized using this strategy. Voltage scaling techniques can address dynamic current and threshold scaling can address leakage. Place and route optimization can improve both power effieciency and maximum performance. A number of advanced circuit design techniques can also address power efficiency.

In traditional CMOS operation, power P is proportional to C*f*V^2 (C capacitance switched per clock cycle, f frequency of switching, V is the main voltage voltage). If you double the number of cores and half their frequency then the total capacitance doubles while the f*V^2 term decreases by 1/8: lowering f allows us to proportionally lower V because we need less potential to charge up a capacitor over a longer period.

A circuit designer will often use the latency of an inverter as their unit of propagation delay. For example, a combinatorial unit may have a delay equivalent to 10 inverter delays. If the system clock is generated by a ring oscillator composed of a series of inverters, then the propagation delay of each inverter will increase as we lower the main voltage. Thus, lowering the main voltage also lowers the ring oscillator frequency. Since the combinatorial paths in the circuit are in units of the inverter delay of the ring oscillator, all of the elements in the circuit will still operate with appropriate relative timing after the supply voltage is lowered.

Since the transition speed of a circuit is dependent on the threshold voltage (see pp 15-18), when we lower our clock frequency, we may also raise our threshold voltage to decrease the leakage current. To address static leakage circuitry multithreshold CMOS techniques may be used along with power enable circuitry. However, multithreshold CMOS will not allow us to decrease leakage dynamically in frequency scaling situations. A while back I made a spreadsheet model of the leakage current (Calc ods format) to demonstrate the benefit of threshold voltage scaling. The threshold voltage is a function of the body bias of a transistor so additional fabrication steps are required to make this variable. Both Xilinx and Altera have incoporated threshold scaling in their latest FPGAs.

When the supply voltage is lower than the threshold voltage, a CMOS circuit operates in subthreshold mode. Subthreshold switching allows for very low power operation for low speed systems. A major issue with subthreshold circuit design is the tight dependency on parameter accuracy: subthreshold drain currents are exponentially dependent on threshold voltage so small parameter variations can have extremely large effects on the system design. This increases the cost of testing devices and decreases the yield.

As the thickness of the gate dielectric decrease, gate leakage current increases due to the tunnelling of electrons through the dielectric. "High-K" dielectrics addres this issue; Intel uses Hafnium instead of SiO2 in their 45-nm process. Optimal gate thickness for gate leakage depends highly on the expected operating temparature and the supply and threshold voltages.

One of the main benefits of FPGA design is their versatility in a range of operation conditions. It is suboptimal to use the same circuit in a variety of different regimes: it is best to optimize a circuit around a small operating range. Thus we should expect high performance devices to be different animals from the low power devices. In some systems it makes sense to use two separate chips: one for high power, high speed operation and another for low power, low speed operation. This is starting to be a common practice for laptop GPUs.

A major cost of distributing work is moving data; this can be addressed using a place-and-route optimization to minimize the signaling distance required for communicating processes. Shorter communication paths can translate into increased power efficiency or latency optimization. When optimizing for latency, the optimization goal is to minimize the maximum latency path. In power optimization, the activity factor for each wire has to be accounted for, so the goal is to minimize the weighted sum of activity times wire-length.

To improve the total interconnect lengths, 3-D integration can be used to stack circuit elements. In three dimensions, it is possible to cut the total amount of interconnect in half. Circuits may be stacked using wafer bonding or epitaxial growth however both processes are expensive. A major concern with 3-D integration is heat removal. IBM has demonstrated water cooling of 3-D intgrated chips. The yield of a wafer bonded circuit is dependent on the defect density on each bonded component. In order to address this issue, defect tolerance must be incorporated into the system design. Another issue to consider is the need for 3-D place-and-route tools.

One of the most costly wires in a system is the clock, which has high activity and has tenticles spanning an entire chip. Clock distribution power is often a double digit percentage of the total system budget. Asychronous circuits operate without a clock, using handshakes to synchronize separate components thereby eliminating the cost of clock distribution.

Adiabatic circuitry uses power clocking and charge-recovery circuitry to asymptotically eliminate switching power as the switching time increases. Combined asynchronous, adiabatic logic uses the asynchronous component handshake as the power clock.

With a number of different technologies available to address power concerns, how can the digital designer rapidly explore a number of architectural possibilities? Automation tools need to be endowed with the ability to transform a digital design to a low-power subthreshold implementation or a high speed circuit with dynamic supply and threshold scaling. These tools need to be aware of the power, speed and manufacturing tradeoffs associated with each of these semiconductor technologies. This will almost certainly require multiple vendors' tools playing nice with eachother.