tag:blogger.com,1999:blog-275402312012-01-26T23:13:01.395-08:00This blog is a notebook of my thoughts on parallel programming and accelerated computing. The instruction stream is deprecated: parallel programming is a spreadsheet.Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.comBlogger1031100tag:blogger.com,1999:blog-27540231.post-26905142381054989112012-01-26T23:12:00.000-08:002012-01-26T23:13:01.405-08:00

I noticed Altera announcing OpenCL support for FPGAs. Here's a paper and some slides on it. I also noticed a blog pop up last week about doing OpenCL on Xilinx. There's also been work on a CUDA->FPGA system called FCUDA from a group from UIUC and UCLA (here's the longer paper on FCUDA). So hardening GPU-designed algorithms is now at least an idea, and possibly a good one. This will enable CMOS

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-24975062816455333112011-10-24T23:03:00.000-07:002011-10-25T22:00:38.052-07:00

The TV space is ripe for disruption, and I keep seeing speculation about an Apple Television. In his biography interviews, Steve Jobs claimed to have "finally cracked" the TV user experience.Last week I presented my start-up ZigFu at the Microsoft Venture Capital Summit and said that motion-control technology like Kinect will be as disruptive to the TV as the remote-control or possibly even color

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-24283012174417563952011-08-24T01:36:00.000-07:002011-08-24T02:15:22.493-07:00

Well, the cat's out of the bag. We've been doing YCombinator this summer developing a motion apps company we're calling ZigFu. Something's gotta pay for all the lasers... Today was the YC demo day and we got some nice press today in GigaOM and Forbes which put us on their short-lists. And that's one demo day down... still another one tomorrow, but now they'll already be anticipating something

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com3tag:blogger.com,1999:blog-27540231.post-88612117394712664172011-03-11T00:31:00.000-08:002011-03-11T01:09:37.983-08:00

I went to an interesting discussion called "Big IT meets Big Web" today hosted by Battery Ventures which brought together a bunch of nerds to talk about the harmonic convergences of IT and Web worlds and deploying services in the cloud. One idea that struck me, was that many of these companies have huge data stores that are never erased. This means we have too many features in the magnetic disks

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-64632054681301682532011-03-02T20:27:00.000-08:002011-03-02T20:30:03.981-08:00

( tinkerheavy.com ) Using Kinect to make Little Red Riding Hood cut up stuff. Fruit Ninjas and Veggie Samurais better get ready for the Sushi Wars.I'm using the Object Slicer package and my Unity wrapper for OpenNI.NET / Kinect.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-36299902465133243392011-01-27T01:15:00.000-08:002011-01-27T01:16:38.382-08:00

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-89717805410393497672011-01-23T04:26:00.000-08:002011-01-23T04:27:46.654-08:00

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-58643858316288750072011-01-21T01:21:00.000-08:002011-01-21T22:05:47.081-08:00

(tinkerheavy.com) This is a demonstration of the Unity wrapper for OpenNI. My skeleton is tracked as I move in front of the Kinect. My feet are rigid-bodies that can kick the boxes. The boxes are also carryable if two hands interact with it simultaneously.If you already have OpenNI+NITE working with your kinect, the binary for this project (pc and mac) is here:http://tinkerheavy.com/

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-76464547739347122002010-12-29T19:30:00.000-08:002010-12-29T19:33:46.695-08:00

I've been hacking the kinect for the last few days. This Little Red character was developed for an upcoming iPad interactive story from my company Tinker Heavy Industries. We've done this with a few other characters. There are some issues with the joint orientation which means my arm goes up and her arm goes down...

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-85637885848157857522010-11-23T02:53:00.000-08:002010-11-23T04:32:46.523-08:00

/. points to this article which says that Intel is putting together an Atom and an FPGA into a single package and selling it for somewhere in the $61-100 range in lots of 1000. This is Intel competing with ARM for the embedded space. We all saw the tighter integration of x86 and FPGA coming 5 years ago when hard PowerPC started finding their way into Xilinx V2 Pros. Achronix is already using

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-59111903352341170832010-11-17T03:27:00.000-08:002010-11-17T14:06:46.136-08:00

Yesterday I was saying we'll see crypto cracking on EC2 with GPUs. In addition to writing it on this blog, I enthusiastically proposed it to friends who are into this sorta thing and of course we then discovered that someone already did it so we lose all novelty points now and should just go back to thinking about how to make money using cloud based GPUs.I've been writing about this for five

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com4tag:blogger.com,1999:blog-27540231.post-67093455388053074182010-11-15T01:45:00.000-08:002010-11-15T01:52:01.423-08:00

Looks like you can get some NVidia Teslas in an EC2 instance now! It seems like Amazon is in the business of selling you a teraflop for $2.10 per hour. This is going to be a big competitive business. I presume I can get a petaflop for a few minutes for under a hundred bucks. Time to start making crypto-crackers!

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-85824563761153707332010-10-26T00:25:00.000-07:002010-10-26T01:06:54.717-07:00

In June, I started a company to make apps for kids. Now Tinker Heavy Industries has its first app in the app store:Another educational app to teach spelling is currently awaiting Apple's approval. Our next app will be an interactive Little Red Riding Hood. We've done some work learning how to build touchable characters and environments. Here's a demo of me playing with Tinker, our

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-49636261072223348612010-07-25T18:26:00.000-07:002010-07-25T18:39:38.333-07:00

Since 2007, I had been developing a PDP-11/70 emulator using Virtex-5 FPGAs for Quickware. The QED970 system is composed of several boards designed to be compatible with legacy hardware specifications. Designing a replica of a 1970's machine revealed a lot to me about the way it used to be; I can hardly imagine designing entire boards with LSI and MSI components to be a Floating Point Unit. An

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-91837469920015145222010-03-02T03:33:00.000-08:002010-03-02T04:10:45.083-08:00

/. linked to this opinion article on AMD, Intel and NVidia in the next decade (full disclosure, I own shares in NVidia). Some of the opinions about OpenCL and CUDA are the same as I expressed in my post about Intel purchasing RapidMind and Cilk. Since I made that post, Intel has decided to abandon plans to release Larabee as a consumer GPU. This was not a big surprise, since Larabee could not

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-15414967459165824562010-02-04T00:04:00.000-08:002010-02-04T00:08:42.490-08:00

EDA SaaS has been a recurring topic on many of the blogs I follow. Harry (the asic guy) wrote about the Blooming of an EDA SaaS Revolution in his first post at Xuropa. He says that the revolution "depends on a confluence of critical technologies." He also writes that the coming revolution will level the playing field allowing smaller EDA firms to compete. The same economics of sharing model that

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-6099623357667927562009-11-02T01:27:00.000-08:002009-11-02T10:41:56.475-08:00

I received an Altium Nanoboard 3000 with the condition that I provide feedback on my experience using it. I hope this information will be useful to Altium and to other Nanoboard users.This will be the first in a multi-part series about using the Altium Nanoboard 3000 with the specific angle of teaching a total FPGA newbie how to get started with this board.A friend of mine is a senior in MIT's

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com7tag:blogger.com,1999:blog-27540231.post-25034649534896347732009-08-24T08:39:00.001-07:002009-08-24T09:26:59.559-07:00

In the past month, Intel has purchased RapidMind and Cilk. I've talked about Cilk on this blog a while ago (post has comments from one of their founders).This was a good move for Intel. It is probably an attempt to make the eventual release of Larrabee less painful for developers. This will help put Intel in the leader seat for parallel programming platforms.What will this mean for CUDA and

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com5tag:blogger.com,1999:blog-27540231.post-35651444021212977382009-08-19T10:31:00.000-07:002009-08-19T13:45:46.300-07:00

It would appear that we have reached the limits of what it is possible to achieve with computer technology, although one should be careful with such statements, as they tend to sound pretty silly in 5 years - John von Neumann, 1949The design goals in parallel computing differ between the embedded multicore market and the high performance computing market. On the one hand, more cores can do

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-71672268898228798272009-07-23T23:14:00.000-07:002009-07-24T13:00:26.881-07:00

It's been a while, I promise I'll post more when I'm finished with my job.The blogs have been buzzing about EDA SaaS ("Electronic Design Automation Software as a Service"). In one of my previous posts on the subject, I argued that the complexity of system design is growing faster than the ability of a reasonable desktop computer and that this will create demand for hosted EDA tools. I also argued

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com9tag:blogger.com,1999:blog-27540231.post-92138682420351071872009-03-11T14:10:00.000-07:002009-03-11T13:33:54.285-07:00

I apologize for not writing in a while. I have been running the DEC XXDP diagnostic tests on my PDP-11/70 emulator. I just finished making integer divide compatible --- not just to spec, but compatible with all the edge cases of the 11/70 model. I'm impressed with how they designed and debugged this sort of thing back in the 60's and 70's. Each bug probably took about a day to diagnose with

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-82440946754399369732008-12-29T20:25:00.000-08:002008-12-29T20:55:02.914-08:00

If you follow this blog, then you've read my ramblings on EDA SaaS. An interesting new advance in this area is http://www.c-to-verilog.com. This website let's you compile C code into synthesizable Verilog modules.Here is a screencast of the service:I've also discovered a few other websites related to EDA, SaaS and "Cloud Computing." Harry the asic guy's blog covers the burgeoning EDA SaaS market

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com4tag:blogger.com,1999:blog-27540231.post-57459668481823588562008-12-05T11:23:00.001-08:002008-12-05T11:59:29.996-08:00

/. points to an IEEE Spectrum article title "Multicore Is Bad News" which discusses the bottleneck associated with getting data from memory into the many cores of a multicore processor.This is primarily an issue with our programming model we are trying to force on the hardware and not a problem with the real capacity of such hardware. The article specifically says that many HPC processes map

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-32532036997649613742008-11-24T14:18:00.000-08:002008-11-24T13:40:11.569-08:00

An article in the New York Times discusses Steve Wallach's Convey Computer Corporation and their new reconfigurable supercomputer.The Convey machines use FPGAs to augment the CPU's instruction set. From a given FORTRAN or C code, their compiler tools create a "personality," which is Convey's way of re-branding the term "configuration."Steve has a great quote on his site, which sums up everything

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-69693192551600217982008-11-11T13:53:00.000-08:002008-11-11T21:28:49.353-08:00

Spectrum policy needs to be re-evaluated in the 21st century. The expansion of the Internet as an organizational model destroys one-way, hierarchically controlled mediums. A Wired article earlier this year observed that the nature of the Internet is to make everything it touches tend to gratis. The Internet and the wireless world are now inextricably linked by devices that support both free

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-81742420474519846362008-10-17T21:55:00.000-07:002008-10-17T07:34:03.160-07:00

Doug Amos from Synopsys wrote at article in FPGA Journal about the Timing Closure problem comparing it to whack-a-mole.I just got through a painful timing closure process. I feel like I came out of a month-long coma. I'll share some anecdotes about the experience to help people in the same situation.The "Post-Map" results are never good enough for timing. You will want to run Place-and-Route so

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-29800102798057260662008-09-22T22:29:00.000-07:002008-09-23T09:32:07.028-07:00

A freshly rebranded Catalyst Accelerated Computing went to the High Performance on Wall Street conference today. The usual suspects were present. Speedup results all seemed to match the gender ratio at supercomputing conferences.FPGAs got bashed in an early session. "It's hard to find people to program FPGAs" came up at least twice during the conference (we consult!). I heard, "threads are the

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com4tag:blogger.com,1999:blog-27540231.post-12339384517657115232008-09-17T14:35:00.000-07:002008-09-17T14:42:28.695-07:00

Congratulations to Achronix on announcing availability of their FPGAs and development boards. The 65nm Speedster reports a 1.5 GHz max internal throughput rate and a ton of I/O. The important technology Achronix is introducing to the market is their high-throughput asynchronous pipelining technique. There are numerous white papers on the Achronix site and research papers from the from their days

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com3tag:blogger.com,1999:blog-27540231.post-35685613246208938822008-09-04T06:56:00.000-07:002008-11-11T14:42:59.754-08:00

An HPCwire article titled "Compilers and More: Parallel Programming Made Easy?" by Michael Wolfe presents a gloomy outlook for parallel programming:Every time I see someone claiming they've come up with a method to make parallel programming easy, I can't take them seriously. People you don't take seriously may take you by surprise. I think the computing industry suffers from the "faster horse"

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com7tag:blogger.com,1999:blog-27540231.post-51644942291640169182008-08-29T07:32:00.000-07:002008-11-28T00:13:23.747-08:00

Prescience is a quality of those who act on it:Building very-large-scale parallel computing structures requires simulation and design-cost analysis whose associated optimizations are MegaHard problems (yes, I'm re-branding NP-Hard). A Software-as-a-Service (SaaS) provider of vendor-neutral simulation, synthesis, mapping, and place-and-route tools could change the electronic design automation

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com5tag:blogger.com,1999:blog-27540231.post-45028489288652244132008-08-24T16:50:00.000-07:002008-08-25T11:51:20.634-07:00

A month ago, Charles Leiserson wrote a post on the Multicore Blog at Cilk Arts called "The Folly of DIY Multithreading." He provides pthreads and Cilk implementations of a parallel fib() function and offers great advice in his article: "Building a concurrency platform from scratch is a mountain to climb." Professor Leiserson mentioned the Therac-25 radiation therapy machine in his post. In 6.033,

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com5tag:blogger.com,1999:blog-27540231.post-6165966271588055842008-08-12T01:12:00.000-07:002008-08-19T13:49:24.482-07:00

(edit 8/19) The judge has lifted the gag order today. (end edit)/. points to an article about a court issuing a temporary restraining order to block a Defcon presentation by a group of MIT students that hacked the Boston T Charlie Card system. Not only can they print their own magnetic-striped cards with up to $655.36, but they can also crack the RFID cards using now-widely-known NXP MiFare

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-30815856099883779162008-07-24T20:22:00.000-07:002008-07-24T23:20:22.496-07:00

In this demo I will show you how to use the RhoZeta Python-Excel bindings to create a non-blocking assignment spreadsheet iteration thread and an OpenGL window to draw cells. This older demo shows more Python evaluate-able code in Excel spreadsheet cells with RhoZeta. Feel free to leave comments and suggestions for future demos.RhoZeta is a Python spreadsheet language with Excel bindings to allow

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-30385146910686714072008-07-21T22:00:00.000-07:002008-09-04T07:11:51.793-07:00

OpenFPGA forked a child called Open Accelerator to organize activities in open accelerated computing. Sounds like my business plan. Let me talk about the hard problem: partitioning.If you're like me, when you got your heterogeneous supercomputer out of the box, you probably produced some mixture of OpenGL, CUDA, Verilog, pthreads or spethreads, Python and duct-tape. We'll get back to the

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-68412309272019319252008-07-13T21:34:00.000-07:002008-07-15T08:20:21.986-07:00

For this entry, I'm going to take a departure from the usual microelectronics and HPC topics and focus on power electronics topics on which I have been keeping .. current (forgive me).UltracapacitorsAccording to Wikipedia, Lithium Ion batteries can store 160 Wh/kg or 576 kJ/kg with maximum power output of 1800 W/kg. The wiki page on ultracapacitors indicates 120 Wh/kg as a comparison point for

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-27065197497983567152008-07-01T11:25:00.001-07:002008-07-01T13:41:22.078-07:00

Another Israeli FPGA guy named Eli Billauer produced a video explaining how to use FPGA Editor. Now that you watched that video, load up FPGA Editor and click on "Help -> Help Topics" to compare your learning experience. Video feature documentation is a great project for an intern. FPGA Editor should feel more like Google Maps. Consider the application specifcation for FPGA Editor and Google Maps

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-64256465209008539862008-06-18T07:15:00.000-07:002008-06-18T13:54:39.077-07:00

Yesterday I wrote about the GFlops/Watt performance numbers for AMD's new GPGPU and ClearSpeed showing 2-2.5 GFlops/Watt -- It looks like Clearspeed has a new card that does 4 Gigaflops/Watt at double precision.NVidia has a new Tesla too. According to the FPGA Journal article you can buy 4 TFlops consuming only 700W or 5.7 GFLops/Watt (It's unlcear if the numbers from FPGA Journal are specs for

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-65365152812231323982008-06-17T14:20:00.000-07:002008-06-17T16:32:02.512-07:00

HPCWire reports on AMD's latest GPUs clocking in with 200 GFlops double precision performance under 150 Watts or 1.33 GFlops/Watt. That translates to a double precision petaflop for .75 MWatts compared to the RoadRunner which consumes 3 MWatts. The AMD GPU is about 2-3 times the peak GFlops/Watt FPGA floating point performance numbers, though I speculate the new Altera Stratix IV may be

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-19533901154731064762008-06-12T12:44:00.000-07:002008-06-12T14:55:44.163-07:00

A blog by David Pellerin of ImpulseC fame called "Reconfigurable, Reconshmigurable" links to Vhayu's announcement of a compression IP for FPGA accelerated ticker systems.To me, the most interesting part of the article is:"Some Wall Street executives interested in using FPGAs to accelerate applications, or portions of them, however, have expressed the concern that it's hard to find programmers who

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-33879291220751091622008-06-09T00:14:00.000-07:002008-06-09T01:25:18.017-07:00

A Petaflop of Cell Processors made the NY Times. Highlights of the article: 12960 total Cell chips with (9*12960)= 116640 cores.The article tries twice to turn the supercomputing top-spot as an issue of national pride. It also discusses the difficulty in programming these devices and how the next generation of consumer products will require programming paradigms for massively multicore hardware.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-73170791483062819122008-05-21T09:47:00.000-07:002008-05-21T10:07:37.406-07:00

In September I wrote:To optimize for static currents, using dynamic threshold scaling (modulating the body bias voltage of the chip) along with dynamic voltage scaling [for active power] seems to be a viable technique. Here's a spreadsheet model (ODS original) for leakage current in a transistor varying Temparature, power and threshold voltage across a reasonable range.According to this FPGA

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-70059263173926119972008-05-11T23:29:00.000-07:002008-05-12T02:18:43.394-07:00

Digital system designers of FPGAs and ASICs alike become extremely familiar with the place-and-route problem during late-night moments of desperate agony the day before a deadline. Place-and-route is about to become relevant to a very new market as the distinction between FPGA and multicore chips turn into a question of granularity. As we increase the number of cores on a chip, the placement of

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-8775002940004373022008-04-09T00:07:00.001-07:002008-04-14T13:47:29.722-07:00

Kevin Morris over at FPGA Journal wrote a really good entry about the evolution of FPGA design and how the tools always target the intended market--even if they don't know the underlying execution engine is a reconfigurable array.So if you want to make a product for the finance dudes, then you're building a spreadsheet--conveniently familiar reconfigurable array. The Accelerator thinks

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-38854804373753780102008-03-31T15:02:00.000-07:002008-04-02T19:10:13.262-07:00

To add to my RhoZeta post from a few weeks back, I thought I'd add an example CellManager. This code demonstrates how to make a Non-Blocking cell manager on a RhoZeta sheet, and how to spawn such a thread for the ActiveSheet in Excel. If you add this to the RhoZeta.py, run the code, and then type "NBCM = NBActiveSheet()" into the PythonWin interactive console you will create a non-blocking style

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-58729623848596386342008-03-28T15:24:00.000-07:002008-03-31T18:07:48.046-07:00

My last post got 40x my usual traffic. Apparently Python Spreadsheets is a hot topic. It also looks like reconfigurable dataflow networks aren't popular under the moniker of a four letter acronym. When you call it a hardware spreadsheet, a 2-D tiled array of functional blocks is suddenly a whole lot more more accessible.A few posts back I recounted the tale (and linked to papers that agreed) that

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com3tag:blogger.com,1999:blog-27540231.post-71040003010662157952008-03-17T17:13:00.000-07:002008-04-18T09:45:27.360-07:00

(see http://catalystac.com/trac for latest code source)Resolver Systems sells a product that does Python with a spreadsheet UI. Resolver uses their own spreadsheet frontend. Here's a demo of how to add Pythonability to Excel. This code is buggy and barely tested and its only a small part of what is an even buggier master's thesis. This demo will show you how to synchronize the visible range in

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com5tag:blogger.com,1999:blog-27540231.post-41547898697702709632008-03-07T14:38:00.000-08:002008-03-07T16:06:50.521-08:00

Doug O'Flaherty joins Joe Landman and I in trying to sort out what is going on in accelerated computing in blog form. More synchronized neurons is probably a good thing. His blog title, "Lead, Follow, or..." begs a good question. The first thing to sort out: are we making waves, riding waves or just blowing bubbles? Considering the recent trend of bus-standard openness is his baby, I wonder if he

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-57348425446965616552008-03-06T11:50:00.000-08:002008-03-06T12:04:37.066-08:00

Slashdot has a link to an article by Peter Rakos demonstrating how to use Excel to power a 3-D graphics engine.He touches upon the paradigm shift associated with the spreadsheet dataflow programming model in comparison to traditional sequential imperative programs.If you've been following my blog you know that my master's thesis argues that a spreadsheet model supporting various sheet calculation

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-13399825402871510122008-02-27T13:29:00.000-08:002008-03-03T12:56:56.963-08:00

FPGA Journal recently published an article by Michael R. D'Amour of DRC Computer titled "Reconfigurable Computing for Acceleration in HPC." It's refreshing to see other FPGA computing enthusiasts populating the internet. The article discusses the marketable benefits of FPGA accelerators and the barriers this field has traditionally faced in its attempts to break into the mainstream. Early in his

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-709225704975132632008-01-16T09:00:00.000-08:002008-01-16T14:04:31.968-08:00

Sup. Still building a PDP-11 for Ontario Power Generation. I also have DRC Computer with an FPGA and a webcam doing image recognition and motion tracking. We're recruiting people for Catalyst Accelerated Computing if you want to have some fun.Here are my Tech Predictions for 20081) P2P Live Video Streaming Goes HD. A cheap dongle will connect your HDMI TV to the internet: "vendors of

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-269086711044382542007-10-08T08:07:00.000-07:002007-10-08T08:37:58.815-07:00

As part of my "anything you can do, I can do in Excel" crusade, I made a spreadsheet to compute the Mandelbrot set (2.5 MB file). This takes roughly 5 seconds per iteration on a single-core Pentium 4 at 2.6 GHz. Excel also seems to consume 128 MB of memory to compute the 400 x 350 x 2 sheets of cells (compare to 28 MB just to run Excel). The slowness and memory overhead (probably related) of

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-87641875338948849402007-09-15T01:59:00.000-07:002007-09-15T12:49:00.443-07:00

The purpose of this entry is to dispell the meme that increasing server utilization is a viable long term approach to power management. The dominant paradigm is that virtualization technology will allow you to increase your server utilization and therefore allow you to improve total performance per watt. White papers from AMD and Intel both discuss consolidation as a means to data center power

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-47411778121043747182007-09-10T09:40:00.000-07:002007-09-23T18:23:17.065-07:00

In my last blog entry, I introduced the spreadsheet parallel programming model that I will be evangelizing for the next several years. The goal of this entry is to contrast the spreadsheet programming model with existing attempts at C-like parallel programming environments. I argue that one-dimensional von Neumann languages are insufficient for expressing the objectives of a parallel program

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com5tag:blogger.com,1999:blog-27540231.post-37761546949629150812007-09-05T08:10:00.000-07:002007-09-06T11:33:31.333-07:00

"What is a von Neumann computer? When von Neumann and others conceived it over thirty years ago, it was an elegant, practical, and unifying idea that simplified a number of engineering and programming problems that existed then. Although the conditions that produced its architecture have changed radically, we nevertheless still identify the notion of "computer" with this thirty year old

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com5tag:blogger.com,1999:blog-27540231.post-3859917374760012482007-08-08T20:41:00.000-07:002007-08-08T21:20:19.482-07:00

I haven't updated this blog in a while. I've been traveling and writing a thesis full of monadic deliciousness and behavioral invariant transformations--coming soon. I started a job last month making a PDP-11 emulator at Quickware. There's probably a few hundred of us who are watching the accelerated computing meme spread. It is catching on, there's probably a few dozen of us ready to put our

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-59214383295225246172007-04-25T08:49:00.000-07:002007-04-25T08:50:41.064-07:00

Joe Landman over at scalability.org has written up a white paper for AMD on accelerated computing technology.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-21563935773250049672007-01-26T14:58:00.000-08:002007-01-27T01:47:56.325-08:00

Many recognition systems work by applying transformations on input data to map a feature space to a more "friendly" feature space. The transformations are generally destructive, non-reversible filters (ie edge detection or color removal in video, frequency selective filtering in audio). This implies a destruction of information in the signal path: by filtering data we reducing the variance of

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-90120903692406562742006-12-26T22:55:00.000-08:002007-01-03T23:26:50.101-08:00

Last semester, some of my classmates and I worked on extensions to Bluespec for Prof. Arvind's class on multithreaded parallelism and compilers. Bluespec's site probably has an overview of the languages ideas, but I'll sum them up here. Bluespec consists of modules which contain registers, rules and methods. A register is a mutable state container. A rule is a guarded atomic action. A guard

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-32263744593162416332006-12-24T14:56:00.000-08:002006-12-24T15:06:51.319-08:00

Polyphase decomposition is a method of transforming a filter into k filters running at 1/k of the sampling rate. The benefit of polyphase decomposition is that reducing the sampling rate of a filter by a factor of k, reduces the power required to implement the filter by a factor of k^3. Of course if we require k times more filters to implement the system, we may only get a k^2 power benefit. I

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-30989657008507900112006-12-01T00:49:00.000-08:002008-03-02T01:16:08.640-08:00

I've been reading a bunch of papers about Adiabatic, Asynchronous Logic systems and Optical interconnect and switching. These seems like three interesting methods that will alleviate the speed / power tradeoff.When most people in the computing world hear "SOA" they think service oriented architecture. For the real EE geeks, Semiconductor Optical Amplifier may come to mind. Optical circuits

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-7985144095606136782006-11-24T23:14:00.000-08:002006-11-24T23:52:25.724-08:00

Catalyst Accelerated Computing has a website. Well sort of. We submitted our executive summary into the MIT $1K competition on Tuesday. We're going to build prototype applications over January. I've been doing my research into the other companies in the "accelerated computing" arena: the best way to stay ahead of the competition is to keep a good scoreboard. That and midterms is why I haven't

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1162545035101999632006-11-03T00:22:00.000-08:002006-11-03T01:10:35.706-08:00

I have a test in computer archi-torture tomorrow and did a problem that asked us to determine the minimum number of cycles to execute a typical iteration of a particular loop on a superscalar processsor with out of order execution under different assumptions. In the "best case" we were allowed to use as many functional units and memory ports as required and are allowed to fetch and commit as

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1161727378063133852006-10-24T14:36:00.000-07:002006-12-27T09:09:44.240-08:00

I have read this article in the economist about the economics of sharing. I also read this paper by a Yale Law professor referenced in the article.The internet has made essentially free the "cost-of-distribution" of accessing extra computing power for things as SETI@Home and file sharing networks. In these cases the resource being distributed is essentially free. In contrast, an open source

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1161328202170819262006-10-19T22:41:00.000-07:002006-10-20T00:25:38.426-07:00

I've been hearing a lot about Globally Asynchronous Locally Synchronous (GALS) systems since Ambric made their announcements. They say their chip architecture simplifies parallel processing. I'll refernce a previous post on why reconfigurable computing hasn't caught on yet.Anyway so more on GALS. GALS is nice because it eases clock distribution which consumes a large portion of the power on

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1161306633937876002006-10-19T18:07:00.000-07:002006-10-19T18:10:33.950-07:00

My friend Joe Presbrey got himself interviewed. We're working on a distributed computing project right now--distributed processing over AJAX. More to come soon. Joe is watching me type this so I have to make sure I don't put anything stupid in here about Bill Cosby.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1160555050358166262006-10-11T00:37:00.000-07:002006-10-11T08:00:47.336-07:00

Most companies that wish to champion the next great paradigm shift to reconfigurable computing fail because they are only seeking to make hardware. They will try to attract developers by listing off potential applications for their hardware and reasons why their chip is going to take over the world. Companies that really are headed for broke fast will try to differentiate their reconfigurable

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1159910513716492092006-10-03T14:20:00.000-07:002006-10-03T14:32:08.593-07:00

I am working on a paper. Here is a draft.Most profiling tools only consider execution time on a single CPU or a homogeneous array. What metrics are useful for profiling an application on a heterogeneous and reconfigurable platform? I offer the unit GOPS/$ as a metric for computational efficiency. GOPS stands for “billions of operations per second” and is dependent on the application. TeraFlops,

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-1159726916401133122006-10-01T10:51:00.000-07:002006-10-01T13:19:18.910-07:00

Since returning to MIT, I've been getting some friends together to build computer systems on heterogeneous fabrics. There really isn't a good framework for load balancing on anything but symmetric multiprocessor environments, and we really need a good way to profile and partition applications across multicore, Cell, GPU and FPGA environments.Of course the question of which accelerator to use is

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1159536136454896762006-09-29T06:21:00.000-07:002006-09-29T06:36:42.090-07:00

article in the register. another article in the register."The end result will likely be a multi-core world where the common general purpose cores of today sit alongside FPGAs, networking products and other co-processors tuned to handle specific tasks at remarkable speeds."

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1159340131339634972006-09-26T23:33:00.000-07:002006-09-26T23:55:31.356-07:00

Slashdot's been talking about multi-core again. Someone brought up FPGA in there too which is always nice. A lot of people wonder what OS support and software support for multi-core will look like. I wonder this regularly, and I think the answer is that we should start to treat multi-core processors not too differently from FPGAs.I think in terms of amortized efficiency benefits, it is likely

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1158846887202040552006-09-21T06:52:00.000-07:002006-09-21T06:54:47.213-07:00

Someone else agrees. Went to the $100K team-building dinner yesterday. I should minimize the number of acronyms in my business plan. FPGA sounds scary. Accelerate does not. DVS sounds scary. Adaptive power management does not... yada.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1158772965361407712006-09-20T10:15:00.000-07:002006-09-20T10:22:45.406-07:00

I just found a paper discussing Scheme compilation to hardware. I have a fairly decent Scheme -> LUT compiler at this point, but there are tons of things I haven't gotten to yet. I hope to have the system ready to demo by the end of September.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1158699547899052182006-09-19T13:11:00.000-07:002006-09-19T13:59:08.236-07:00

Last semester I wrote some of the basic components of a lattice processing simulator. These past couple weeks have been full of digressions, but I'm back to coding 4-8 hours a day. I've been developing a Scheme Web Server and XMLHttpRequest handler which should enable web-based development for a fabric of cells (email me if you want the code in its current form). I had some problems with POST

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1157953800522725202006-09-10T22:26:00.000-07:002006-09-15T10:16:52.263-07:00

I've been thinking of ways to argue for FPGAs in the utility computing market. "Cost effective computing" is easier to sell now that multi-core offerings are actually "slower" (in terms of clock speed) than previous chips. Intel and AMD already have us all warmed up to the idea that having more cores is better than faster cores. This makes it easier to market FPGAs as compute elements.I think

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1157630334882725122006-09-07T04:47:00.000-07:002006-09-07T04:58:54.913-07:00

The utility computing market is set to grow extremely rapidly in the next few years. A guy from Sun spoke to my 6.891 lecture last year saying he was spending his time trying to figure out utility computing. Can a group of MIT students start a company and beat the big players in this market? In the utility computing market, the major objective of computing providers and consumers will be to

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1157309265529460062006-09-03T11:36:00.000-07:002006-09-03T11:47:45.540-07:00

By enabling perfect substitution of computing products, virtualization enables the commoditization of the computing industry. High bandwidth connectivity enables the delocalization of computing hardware by allowing large amounts of data to be quickly stored and retrieved remotely.Reconfigurable computers will win in settings where the costs associated with transistioning an application to a

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1157126016010072142006-09-01T08:40:00.000-07:002006-09-04T20:42:17.280-07:00

two articles caught my attention today:The CTO of Intel gave a talk at Stanford last week looking to stimulate multithreaded software development. It is not surprising that Intel needs software to target it's multi-core offering. The problems for software developers is to design scalable systems so that as Intel cranks out more and more cores on their chips, we don't have to undergo a software

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-1156917534502324122006-08-29T22:29:00.000-07:002006-08-29T22:58:54.560-07:00

Today was my last day at Xilinx. I fly away from the west coast tomorrow morning and head back to MIT to begin my year as a grad student. Hopefully I will emerge unscathed.I've been thinking a lot about the implications of software virtualization to FPGA computing. I'm intrigued by the idea of implementing a hypervisor in a tightly coupled FPGA/CPU system. I imagine a system with an FPGA

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1156309959738817242006-08-22T22:11:00.000-07:002006-08-22T22:41:35.330-07:00

Starting to think out loud:Taking advantage of paralellism is a necessary step for the advance of computing. Chip-multiprocessors (CMP) and FPGAs enable concurrent computation paradigms. CMPs allow for thread-level parallelism (TLP), where each core contains an instruction cache consisting of the current set of supported functions. Reconfigruable datapath arrays allow for networks of fixed

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1156180673613779282006-08-21T10:12:00.000-07:002006-08-21T10:17:53.633-07:00

A few weeks ago I wrote an entry titled "Intel, AMD, Sun... Xilinx." In light of a new press release, It would see a more appropriate title is: "AMD, Sun... Altera"

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1155673564499058412006-08-15T13:09:00.000-07:002008-06-10T09:35:10.361-07:00

Achronix plans to deliver FPGAs that run at gigahertz speeds over a wide range of conditions. They have limited information on their site, but they claim to be using some asynchronous design method, which begs the question: what is being clocked at gigahertz speeds? They got back some silicon prototypes in April and two days later announced a low-power initiative, so I wonder what the power

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1155600234250164472006-08-14T16:48:00.001-07:002006-08-14T17:03:54.253-07:00

I picked up last month's Tech Review and I discovered this startup looking to make chips with 1000 8 bit cores. The RAMP Project and the RAW project are extremely relevant to Rapport. Looks a lot like they're taking the RAW chip commercial... I hope that they don't blow through all of their funding attempting to manufacture a chip without establishing a software development environment and a

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1154584275594850802006-08-02T22:30:00.000-07:002006-08-21T01:43:04.100-07:00

I just started fpgacommunity.com. Since only like 3 people read this blog, I suppose the community will be small :) This along with fpgawiki.com will soon be hosted on a different server (when I get back to MIT) and then I plan to spread the meme through mailing lists and usenet groups. I think if there was a tighter community of FPGA users and developers, launching fpgaos.com as a community

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com3tag:blogger.com,1999:blog-27540231.post-1154387347487057172006-07-31T15:39:00.000-07:002006-07-31T16:09:07.910-07:00

Article discusses the potential for FPGA-targetted software. Touches upon Intel's EPIC project that was supposed to make the Itanium rule the world. I think the problem is that the scope of the Itanium processor pushed it to far out of reach. FPGAs on the other hand have the nice property of sweeping across many markets, price points and even usage patterns (embedded controller, DSP, HPC

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-1154022473326534552006-07-27T10:44:00.000-07:002006-07-27T10:47:53.353-07:00

someone else's blog. another confirmation of what i've been spewing... i especially like this comment: "...there is something decidedly unsexy about High Performance Computing..."a supercomputer with sex appeal... maybe if Apple were to brand it.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-1153893991371785932006-07-25T23:02:00.000-07:002006-07-25T23:06:31.380-07:00

A wiki for reconfigurable computing. feel free to contribute. feel free to rip articles off wikipedia too. I will start to publicize it more (mailing lists, usenet and such) once I take care of the hosting issues.coming soon: fpgaos.com -- As soon as I get back to MIT I will be hosting a website on an FPGA and allow people to actively contribute to the development of the hosting platform.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com2tag:blogger.com,1999:blog-27540231.post-1153784063297823312006-07-24T16:28:00.001-07:002006-07-24T16:34:23.310-07:00

EE Times article asks an interesting question in its last sentence. The answer is "I do." I just need a team of 7 to 10 young (not bound to wives/children) hackers who can work 25 hours a day 8 days a week for the next year. This will also require a bunch of mountain dew and maybe some adult supervision--perhaps a $300,000 in initial funding to buy equipment and pay for the mountain dew.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1153208353197985442006-07-18T00:38:00.000-07:002006-07-18T00:39:13.206-07:00

poppy.snu.ac.kr/~ykim/resume/DATE_05.pdf

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1152865192655650622006-07-14T00:52:00.000-07:002006-07-25T11:42:19.846-07:00

standard press release.been thinking about Virtual Machines and FPGAs. Both of those two terms are increasing in relevance. they will also start to sync up in co-relevance.i've made some headway on my thesis work lately. i'm working on a "parallel evaluator" for scheme right now that uses multiple evaluators each with their own strategies.an evaluator consists of:

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1151884282395435892006-07-02T16:50:00.000-07:002006-07-02T16:51:22.406-07:00

article in the register

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com3tag:blogger.com,1999:blog-27540231.post-1149577258630046032006-06-05T22:38:00.000-07:002006-06-06T00:16:47.993-07:00

In anticipation of my impending internship at Xilinx, I have been searching for an appropriate algorithm to accelerate on an FPGA. A good friend of mine in the Broad Institute at MIT sent me an email last week describing the problem of understanding the binding strategies of the transcription factors of human DNA. On many occasions in the past, we have distracted ourselves from homework by

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com3tag:blogger.com,1999:blog-27540231.post-1148788357370060572006-05-27T20:30:00.000-07:002006-05-27T20:52:37.380-07:00

3-D integration is going to become more and more popular in the next few years. I created a thermal cost function for a 3-D FPGA Place and Route last year for 6.374. Prof. Chandrakasan, who taught 6.374, has been researching a 3-D FPGA. I haven't done any further work on it since the class, but I read an article today about integrated cooling which made me think about it again (I've looked into

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1148757917449195222006-05-27T11:54:00.000-07:002006-05-27T12:25:32.713-07:00

Found this article by Ian Page, a researcher in reconfigurable computing and founder of Celoxica. I think he's right on with his observations.

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1148141928458552212006-05-20T08:59:00.000-07:002006-05-20T09:18:49.253-07:00

I've been toying with an IP core that allows me to access the FPGAs reconfiguration port from the internals of the FPGA. I've connected the reconfiguration port to a microblaze core running ucLinux, but I haven't actually got a method to do anything worthwhile. I'd like to get a Linux running on the dual PowerPCs so I can start to Kernel hack it and enable dynamic reconfiguration methods. I'm

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1148140617340955642006-05-20T08:54:00.000-07:002006-05-20T08:56:57.356-07:00

I've often suggested that self-assembled molecular electronics would be in the form of reconfigurable arrays. I found this article to back it up."We've now discovered molecules that act just like reconfigurable logic bits," says Hewlett-Packard's Kuekes. "We are proposing fairly simple devices that can be literally grown with chemistry. Then all the complexity will be downloaded into

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1147832916347132672006-05-16T19:04:00.000-07:002006-05-16T19:35:35.770-07:00

The CTO of Xilinx came to MIT to check out the 6.111 projects and to give a talk on the future of FPGA. He mentioned most of the stuff I babble about in this blog. He discussed the need for better tools to increase the transparency of targetting FPGAs to open the market up to computer scientists (who outnumber us Electrical Engineers by 100 to 1). He also specifically mentioned dynamic partial

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com1tag:blogger.com,1999:blog-27540231.post-1147745011137871772006-05-15T18:51:00.000-07:002006-05-16T09:05:35.390-07:00

One of the problems with most HDLs is that they do not support recursively defined circuits. It's not too hard to make macros for such things in other languages, but as the circuit size gets too large it becomes impractical to implement. However a mechanism for handling such things would be really useful.Recursive functional programs map to recursive structural circuits. We want an

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1147673376316920122006-05-14T22:23:00.000-07:002006-05-16T08:53:04.263-07:00

In order to maintain target independence, I'm building circuit fabrics in Scheme using the digital circuit simulator as outlined in SICP (section 3.3.4).I will eventually want to run "virtual" fabrics on my current reconfigurable computing setup so that I can use the virtual fabric to test the scheduling algorithm. I will end up simulating more complex fabrics and with functional multiplexing

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1147591087658079302006-05-13T23:47:00.000-07:002006-05-14T00:18:07.680-07:00

How do we optimally schedule for an FPGA?One way to look at this problem: we have to schedule circuits A and B with no connection to eachother. Now using only 2 input muxes merge the circuits into one circuit such that if the mux select is 0 then the system behaves as circuit A and if the mux is in 1 then the system behaves as circuit B. Minimize the amount of logic you need without adding new

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0tag:blogger.com,1999:blog-27540231.post-1147589203174407062006-05-13T23:33:00.000-07:002006-05-13T23:46:43.180-07:00

My belief is that a good programming interface for reconfigurable systems will be necessary for future chips. I believe that manufacturing considerations for future nanoscale ICs will proove fault-tolerant fabrics to be the optimal chip structure. Years beyond that amorphous and self-assembing cellular structures are likely to replace the fabrication methods of today. It is likely that these

Amirhttp://www.blogger.com/profile/05436827810418004991noreply@blogger.com0